1. Field of the Invention
This invention relates generally to semiconductor memory units and, more particularly, to dynamic random access memory (DRAM) units. A DRAM unit requires a relatively stable plate voltage for the storage cells to prevent incorrect identification of the logic state represented by the storage cell. The present invention provides for a stable plate voltage even under conditions that can result in plate voltage transients.
A dynamic random access memory (DRAM) includes an array of storage cells 10, a schematic diagram of a storage cell being included as FIG. 1. Each storage cell typically includes a gate element 12 and a capacitor element 14. A control terminal of gate element 12 is coupled to control line 8. Control line 8 is, in addition, typically coupled to control terminals of gate elements of a multiplicity of storage cells, the multiplicity of storage cells coupled to control line 8 generally forming a row in the DRAM unit array of storage cells. Each gate element is typically coupled between one terminal of capacitor 14 and a sense line 6. The sense line 6 is coupled to a column of storage cells 10 in the DRAM memory array of storage cells. The second terminal of capacitor 14 is coupled to a plate voltage terminal 16.
A logic state stored in the storage cell 10 is represented by the amount of charge stored on, and therefore the voltage across, capacitor 14. In the storage or write mode of the storage cell, the control line 8 is activated thereby enabling the gate 12. The logic state to be stored is determined by the charge stored on the capacitor as a result of potential level of sense line 6. In the retrieve or read mode of operation of the storage cell, the control line 8 enables the gate element 12 and the potential applied to the sense line 6 identifies the logic state stored on the capacitor. In DRAM memory arrays, the charge stored on the plates of capacitor 14 can gradually leak off, thereby compromising the ability of apparatus coupled to sense line 6 to determine the logic state of storage element 10, i.e., identify the correct voltage level applied to line 6 when control line 8 is activated. To avoid the degradation of the logic signal, the storage cells 10 in the array are periodically refreshed, i.e., the logic state (or charge on the capacitor) of the storage cell is detected and the charge on the capacitor 14 is returned to a non-degraded value. The non-degraded value of charge thereby provides a correct identification of the logic state by sense line 6 upon activation of the control line 8. (The charge representing the logic level in a storage cell 10 can also be degraded when the storage cell is accessed in the read or retrieve mode of operation and the degraded charge must be restored immediately following the operation resulting in the storage cell access when the logic level is to be maintained in the storage cell 10).
It will be clear that whenever the capacitor 14 is charged (or discharged), a perturbation is transmitted (by capacitive coupling) to the plate voltage terminal 16. A perturbation in the plate voltage can be communicated to other storage cells and can compromise the identification of the logic state represented by the charge stored on the capacitor. In general, because of the large number of storage cells, the perturbation in the plate voltage will be small unless a substantial number of storage cells are accessed simultaneously. Moreover, during initiation of the DRAM unit, when a group of the storage cells have not yet had a definite logic signal stored therein, the charges of the capacitors of that group can be at an intermediate value, and when definite logic signals are stored therein, such as in a refresh cycle, the identification of the logic signals that have already been stored in other groups of storage cells can be compromised through the capacitive coupling.
To minimize the effect of the capacitive coupling of charging a storage cell capacitor on the plate voltage, the size of the energizing source providing power to the array of storage cells can be increased. However, the use of a power supply which is capable of providing the requisite power in all circumstances of large transient conditions is inefficient. In addition, it is desirable to have the power supplied to the plate operate in only an intermittent fashion. The constant operation of the plate supply can result in unacceptable power dissipation, i.e., by the standby current.
A need has therefore been felt for apparatus and an associated method to provide an energizing source for the plate voltage for the storage cells of DRAM units which maintains the array plate voltage within predetermined limits without requiring excessive apparatus. The apparatus and associated method in addition should minimize the effect of plate voltage transients resulting from capacitive coupling of the storage cells on the plate voltage.